Defects identification on semiconductor wafer for yield improvement using machine learning / Pedram Tabatabaeemoshiri
The semiconductor industry underpins modern technology, with its products embedded in almost every electronic device. As semiconductor devices grow increasingly intricate, ensuring their quality and reliability becomes more challenging. Electrical testing is crucial to semiconductor wafer quality...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Published: |
2025
|
| Subjects: | |
| Online Access: | http://studentsrepo.um.edu.my/16000/1/Pedram_Tabatabaeemoshiri.pdf http://studentsrepo.um.edu.my/16000/2/Pedram_Tabatabaeemoshiri.pdf http://studentsrepo.um.edu.my/16000/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | The semiconductor industry underpins modern technology, with its products
embedded in almost every electronic device. As semiconductor devices grow increasingly
intricate, ensuring their quality and reliability becomes more challenging. Electrical
testing is crucial to semiconductor wafer quality assurance, designed primarily to identify
fabrication defects. However, the testing process itself can inadvertently introduce new
defects that may go undetected by subsequent inspection methods such as manual and
visual inspection. When these defects escape detection, defective wafers may reach
customers, leading to rejection and return to the manufacturer, resulting in significant
yield losses and operational inefficiencies. This study addresses the urgent issue of
detecting hidden defects in semiconductor wafers that conventional methods overlook.
This work presents a novel graph-based semi-supervised learning (GSSL) algorithm
designed for wafer defect detection. The proposed methodology involves collecting wafer
inspection data, extracting relevant features, and applying the GSSL algorithm to identify
the hidden defects. The approach constructs a graph representation of the wafer,
leveraging its physical layout and test configuration, and integrates domain-specific
knowledge. The method uses weighted edges to represent the likelihood of defect
propagation between dies, optimized through extensive experimentation, followed by an
iterative label propagation process to uncover hidden defects. Experimental results
demonstrate the effectiveness of our method, achieving a 68% accuracy in detecting
hidden defects across multiple product categories in real-world semiconductor
manufacturing environments. The algorithm showed consistent performance across
different wafer types and test configurations, outperforming traditional detection methods with improved computational efficiency. This study offers valuable insights into the
semiconductor industry, providing an advanced tool to enhance yield management and
quality control processes.
|
|---|