Smart transducer interface module (main state machine VHDL) / Marina Haryati Mohammad
This project is about the development of Smart Transducer Interface Module in hardware. The IEEE1451.2 smart sensor approach specifies a 'plug and play' capability in a transducer module, which is achieved through transducer electronic data sheet (TEDS). It specifies a digital interface to...
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| Format: | Thesis |
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2005
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| Online Access: | http://studentsrepo.um.edu.my/11580/1/marina_haryati_0405.pdf http://studentsrepo.um.edu.my/11580/ |
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| _version_ | 1831435846852542464 |
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| author | Marina , Haryati Mohammad |
| author_facet | Marina , Haryati Mohammad |
| author_sort | Marina , Haryati Mohammad |
| building | UM Library |
| collection | Institutional Repository |
| content_provider | Universiti Malaya |
| content_source | UM Student Repository |
| continent | Asia |
| country | Malaysia |
| description | This project is about the development of Smart Transducer Interface Module in hardware. The IEEE1451.2 smart sensor approach specifies a 'plug and play' capability in a transducer module, which is achieved through transducer electronic data sheet (TEDS). It specifies a digital interface to access TEDS and transducer are defined. This STIM will be implemented using VHSIC Hardware Description Language (VHDL). Peak FPGA software. This report will comprise the ST1M phase from the design phase of main state machine until the end of testing phase. |
| format | Thesis |
| id | my.um.stud-11580 |
| institution | Universiti Malaya |
| publishDate | 2005 |
| record_format | eprints |
| spelling | my.um.stud-115802021-07-26T23:12:15Z Smart transducer interface module (main state machine VHDL) / Marina Haryati Mohammad Marina , Haryati Mohammad QA75 Electronic computers. Computer science QA76 Computer software This project is about the development of Smart Transducer Interface Module in hardware. The IEEE1451.2 smart sensor approach specifies a 'plug and play' capability in a transducer module, which is achieved through transducer electronic data sheet (TEDS). It specifies a digital interface to access TEDS and transducer are defined. This STIM will be implemented using VHSIC Hardware Description Language (VHDL). Peak FPGA software. This report will comprise the ST1M phase from the design phase of main state machine until the end of testing phase. 2005 Thesis NonPeerReviewed application/pdf http://studentsrepo.um.edu.my/11580/1/marina_haryati_0405.pdf Marina , Haryati Mohammad (2005) Smart transducer interface module (main state machine VHDL) / Marina Haryati Mohammad. Undergraduates thesis, University of Malaya. http://studentsrepo.um.edu.my/11580/ |
| spellingShingle | QA75 Electronic computers. Computer science QA76 Computer software Marina , Haryati Mohammad Smart transducer interface module (main state machine VHDL) / Marina Haryati Mohammad |
| title | Smart transducer interface module (main state machine VHDL) / Marina Haryati Mohammad |
| title_full | Smart transducer interface module (main state machine VHDL) / Marina Haryati Mohammad |
| title_fullStr | Smart transducer interface module (main state machine VHDL) / Marina Haryati Mohammad |
| title_full_unstemmed | Smart transducer interface module (main state machine VHDL) / Marina Haryati Mohammad |
| title_short | Smart transducer interface module (main state machine VHDL) / Marina Haryati Mohammad |
| title_sort | smart transducer interface module (main state machine vhdl) / marina haryati mohammad |
| topic | QA75 Electronic computers. Computer science QA76 Computer software |
| url | http://studentsrepo.um.edu.my/11580/1/marina_haryati_0405.pdf http://studentsrepo.um.edu.my/11580/ |
| url_provider | http://studentsrepo.um.edu.my/ |