Search Results - Salehuddin F.

Statistical process modelling for 32nm high-K/metal gate PMOS device by Maheran A.H.A., Noor Faizah Z.A., Menon P.S., Ahmad I., Apte P.R., Kalaivani T., Salehuddin F.

Analysis of threshold voltage variance in 45nm n-channel device using L27 orthogonal array method by Salehuddin F., Mohd Zain A.S., Idris N.M., Mat Yamin A.K., Abdul Hamid A.M., Ahmad I., Menon P.S.

Taguchi modeling of process parameters in vdg-mosfet device for higher ION/IOFF ratio by Kaharudin K.E., Salehuddin F., Hamidon A.H., Aziz M.N.I.A., Ahmad I.

Work function variations on electrostatic and RF performances of JLSDGM Device by Kaharudin K.K.E., Zain A.S.M., Roslan A.F., Ahmad I., Salehuddin F.

Design and optimization of 22nm NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Majlis B.Y., Salehuddin F.

Scaling down of the 32 nm to 22 nm gate length NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Elgomati H.A., Majlis B.Y., Salehuddin F.

Application of Taguchi method in the optimization of process variation for 32nm CMOS technology by Elgomati H.A., Majlis B.Y., Ahmad I., Salehuddin F., Hamid F.A., Zaharim A., Apte P.R.

Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A., Hashim U., Apte P.R.

Influence of HALO and source/drain implantation on threshold voltage in 45nm PMOS device by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A.

Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage by Elgomati H.A., Majlis B.Y., Ahmad I., Salehuddin F., Hamid F.A., Zaharim A., Mohamad T.Z., Apte P.R.

Effect of process parameter variations on threshold voltage in 45nm NMOS device by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A.

Optimization of process parameter variability in 45 nm PMOS device using Taguchi method by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A.

Impact of high-k insulators on electrical properties of junctionless double gate strained transistor by Kaharudin K.E., Salehuddin F., Zain A.S.M., Jalaludin N.A., Arith F., Junos S.A.M., Ahmad I.

Unveiling the photovoltaic properties of ETL-free, lead-free, and graphene-based PSC by Jalaludin N.A., Salehuddin F., Arith F., Zain A.S.M., Kaharudin K.E., Junos S.A.M., Ahmad I.

Statistical optimization influence on high permittivity gate spacer in 16nm DG-FinFET device / Ameer F. Rosla … [et al.] by Rosla, Ameer F., Salehuddin, F., Zain, A.S.M., Kaharudin, K.E., Mohamad, N.R., A.H, Afifah Maheran, Haroon, H., Razak, H.A., Idris, S.K., Ahmad, I.

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Application of taguchi method with the interaction test for lower DIBL IN WSix/TiO2 channel vertical double gate NMOS by Kaharudin K.E., Salehuddin F., Zain A.S.M., Aziz M.N.I.A., Ahmad I.

Variability analysis of process parameters on subthreshold swing in vertical DG-MOSFET device by Kaharudin K.E., Salehuddin F., Hamidon A.H., Zain A., Abd Aziz M.N.I., Ahmad I.

Electrical characterization of different high-k dielectrics with tungsten silicide in vertical double gate nmos structure by Kaharudin K.E., Salehuddin F., Soin N., Zain A.S.M., Aziz M.N.I.A., Ahmad I.

Optimization of process parameter variations on threshold voltage in Ultrathin Pillar Vertical Double Gate MOSFET Device by Kaharudin K.E., Hamidon A.H., Salehuddin F., Ifwat Abd Aziz M.N., Ahmad I.

Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Salehuddin F., Mohd A.S., Noor Z.A., Elgomati H.A.