Search Results - Assaad, Maher

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  1. 1
    Novel Hybrid Iterative Learning--Fractional Predicative PI Controller for Time-Delay Systems

    Novel Hybrid Iterative Learning--Fractional Predicative PI Controller for Time-Delay Systems by Arun Mozhi Devan, P, Hussin, Fawnizu Azmadi, Ibrahim, Rosdiazli, Nagarajapandian, M, Assaad, Maher

    Published 2022
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  2. 2
    Design and Modeling of PLL Based CDR for Inter Chip Communications

    Design and Modeling of PLL Based CDR for Inter Chip Communications by Assaad, Maher

    Published 2009
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  3. 3
    CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC

    CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC by Assaad, Maher

    Published 2007
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  4. 4
    20 GB/S REFERENCELESS QUARTER-RATE PLL-BASED CLOCK DATA RECOVERY CIRCUIT IN 130 NM CMOS TECHNOLOGY

    20 GB/S REFERENCELESS QUARTER-RATE PLL-BASED CLOCK DATA RECOVERY CIRCUIT IN 130 NM CMOS TECHNOLOGY by Assaad, Maher

    Published 2008
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  5. 5
    Ultra low power, harsh environment SOI-CMOS design of temperature-sensor based threshold-detection and wake-up IC

    Ultra low power, harsh environment SOI-CMOS design of temperature-sensor based threshold-detection and wake-up IC by Assaad, Maher

    Published 2010
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  6. 6
    Hybrid Harris Hawks with Sine Cosine for Optimal Node Placement and Congestion Reduction in an Industrial Wireless Mesh Network

    Hybrid Harris Hawks with Sine Cosine for Optimal Node Placement and Congestion Reduction in an Industrial Wireless Mesh Network by Abdulrab, Hakim QA, Hussin, Fawnizu Azmadi, Ismail, Idris, Assaad, Maher, Awang, Azlan, Shutari, Hussein, Devan, P Arun Mozhi

    Published 2023
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  7. 7
    Ultra low power CMOS circuits working in subthreshold regime for high temperature and radiation environments

    Ultra low power CMOS circuits working in subthreshold regime for high temperature and radiation environments by Boufouss, Elhafed, Francis, Laurent, Gerard, Pierre, Assaad, Maher

    Published 2011
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  8. 8
    High Performance Tracking Optimal Linear Matrix Inequality-Fractional-order PI for MIMO Processes

    High Performance Tracking Optimal Linear Matrix Inequality-Fractional-order PI for MIMO Processes by Devan, P. Arun Mozhi, Nagarajapandian, M., Anitha, T., Assaad, Maher, Hussin, Fawnizu Azmadi

    Published 2024
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  9. 9
    LMI Based PI Controller Design for a Multivariable System with High-performance Tracking for Non-minimum Phase Systems

    LMI Based PI Controller Design for a Multivariable System with High-performance Tracking for Non-minimum Phase Systems by Nagarajapandian, M., Devan, P. Arun Mozhi, Anitha, T., Srinivasan, K., Assaad, Maher, Hussin, Fawnizu Azmadi

    Published 2024
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  10. 10
    An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC

    An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC by Assaad, Maher, Alser, Mohammed

    Published 2011
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  11. 11
    Design and characterization of multi-color sensor circuit

    Design and characterization of multi-color sensor circuit by Assaad, Maher, Yohannes, Israel

    Published 2011
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  12. 12
    Design and characterisation of ultra-low-power SOI-CMOS IC temperature level detector

    Design and characterisation of ultra-low-power SOI-CMOS IC temperature level detector by Assaad, Maher, Boufouss, Elhafed, Gerard, Pierre, Francis, Laurent, Flandre, Denis

    Published 2012
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  13. 13
    A four-colour optical detector circuit

    A four-colour optical detector circuit by Assaad, Maher, Yohannes, Israel

    Published 2013
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  14. 14
    Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

    Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture by Assaad, Maher, Alser, Mohammed

    Published 2012
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  15. 15
    Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit

    Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit by Alser, Mohammed, Assaad, Maher, Hussin, Fawnizu Azmadi, Bayou, Israel Yohannes

    Published 2012
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  16. 16
    A wide-range programmable frequency synthesizer based on a finite state machine filter

    A wide-range programmable frequency synthesizer based on a finite state machine filter by Alser, Mohammed H., Assaad, Maher M., Hussin, Fawnizu Azmadi

    Published 2012
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  17. 17
    A Miniaturized Metamaterial-Based Dual-Band 4×4 Butler Matrix With Enhanced Frequency Ratio for Sub-6 GHz 5G Applications

    A Miniaturized Metamaterial-Based Dual-Band 4×4 Butler Matrix With Enhanced Frequency Ratio for Sub-6 GHz 5G Applications by ABDULKADIR BELLO SHALLAH, ABDULKADIR BELLO SHALLAH, FARID ZUBIR, FARID ZUBIR, MOHAMAD KAMAL A. RAHIM, MOHAMAD KAMAL A. RAHIM, NOORLINDAWATY MD. JIZAT, NOORLINDAWATY MD. JIZAT, ABDUL BASIT, ABDUL BASIT, MAHER ASSAAD, MAHER ASSAAD, HUDA A. MAJID, HUDA A. MAJID

    Published 2024
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