Search Results - Afifah Maheran A.H.

  • Showing 1 - 14 results of 14
Refine Results
  1. 1
    Optimization of process parameters for threshold voltage and leakage current based on taguchi method

    Optimization of process parameters for threshold voltage and leakage current based on taguchi method by Noor Faizah Z.A., Ahmad I., Ker P.J., Menon P.S., Afifah Maheran A.H., Mah S.K.

    Published 2023
    Article
    Save to List
    Saved in:
  2. 2
    Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method

    Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

    Published 2023
    Conference Paper
    Save to List
    Saved in:
  3. 3
    Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method

    Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

    Published 2023
    Conference Paper
    Save to List
    Saved in:
  4. 4
    Vth and ILEAK Optimization using taguchi method at 32nm bilayer graphene PMOS

    Vth and ILEAK Optimization using taguchi method at 32nm bilayer graphene PMOS by Noor Faizah Z.A., Ahmad I., Ker P.J., Menon P.S., Afifah Maheran A.H.

    Published 2023
    Article
    Save to List
    Saved in:
  5. 5
    Design and optimization of 22nm NMOS transistor

    Design and optimization of 22nm NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Majlis B.Y., Salehuddin F.

    Published 2023
    Article
    Save to List
    Saved in:
  6. 6
    Scaling down of the 32 nm to 22 nm gate length NMOS transistor

    Scaling down of the 32 nm to 22 nm gate length NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Elgomati H.A., Majlis B.Y., Salehuddin F.

    Published 2023
    Conference paper
    Save to List
    Saved in:
  7. 7
    Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor

    Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

    Published 2023
    Conference Paper
    Save to List
    Saved in:
  8. 8
    Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor

    Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

    Published 2023
    Article
    Save to List
    Saved in:
  9. 9
    Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method

    Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Salehuddin F., Mohd A.S., Noor Z.A., Elgomati H.A.

    Published 2023
    Article
    Save to List
    Saved in:
  10. 10
    Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device

    Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device by Afifah Maheran A.H., Menon P.S., Ahmad I., Noor Faizah Z.A., Mohd Zain A.S., Salehuddin F., Sayed N.M.

    Published 2023
    Article
    Save to List
    Saved in:
  11. 11
    Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor

    Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Salehuddin F.

    Published 2023
    Conference paper
    Save to List
    Saved in:
  12. 12
    Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method

    Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Salehuddin F., Mohd Zain A.S.

    Published 2023
    Article
    Save to List
    Saved in:
  13. 13
    Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.

    Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method. by Afifah Maheran A.H., Firhat E.N., Salehuddin F., Mohd Zain A.S., Ahmad I., Noor Faizah Z.A., Menon P.S., Elgomati H.A., Roslan A.F.

    Published 2023
    Conference Paper
    Save to List
    Saved in:
  14. 14
    Threshold voltage optimization in a 22nm High-k/Salicide PMOS device

    Threshold voltage optimization in a 22nm High-k/Salicide PMOS device by Afifah Maheran A.H., Menon P.S., Ahmad I., Yusoff Z.

    Published 2023
    Conference paper
    Save to List
    Saved in:

Search Tools: