Search Results - 56395444600

Statistical process modelling for 32nm high-K/metal gate PMOS device by Maheran A.H.A., Noor Faizah Z.A., Menon P.S., Ahmad I., Apte P.R., Kalaivani T., Salehuddin F.

Modelling of 14NM gate length La2O3-based n-type MOSFET by Mah S.K., Ahmad I., Ker P.J., Noor Faizah Z.A.

High-k Dielectric Thickness and Halo Implant on Threshold Voltage Control by Mah S.K., Ahmad I., Ker P.J., Noor Faizah Z.A.

Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method by Maheran A.H.A., Menon P.S., Shaari S., Kalaivani T., Ahmad I., Faizah Z.A.N., Apte P.R.

Statistical modelling of 14nm n-types MOSFET by Noor Faizah Z.A., Ahmad I., Ker P.J., Siti Munirah Y., Mohd Firdaus R., Mah S.K., Menon P.S.

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Optimization of process parameters for threshold voltage and leakage current based on taguchi method by Noor Faizah Z.A., Ahmad I., Ker P.J., Menon P.S., Afifah Maheran A.H., Mah S.K.

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Process parameters optimization of 14nm p-type MOSFET using 2-D analytical modeling by Noor Faizah Z.A., Ahmad I., Ker P.J., Siti Munirah Y., Mohd Firdaus R., Mah S.K., Menon P.S.

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Vth and ILEAK Optimization using taguchi method at 32nm bilayer graphene PMOS by Noor Faizah Z.A., Ahmad I., Ker P.J., Menon P.S., Afifah Maheran A.H.

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Modeling of 14 nm gate length n-Type MOSFET by Faizah Z.A.N., Ahmad I., Ker P.J., Roslan P.S.A., Maheran A.H.A.

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Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method by Maheran A.H.A., Menon P.S., Shaari S., Ahmad I., Faizah Z.A.N.

Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling by Noor Faizah Z.A., Ahmad I., Ker P.J., Siti Munirah Y., Mohd Firdaus R., Md Fazle E., Menon P.S.

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Process Characterization of 32nm Semi Analytical Bilayer Graphene-based MOSFET by Noor Faizah Z.A., Ahmad I., Ker P.J., Menon P.S.

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Modeling, simulation and optimization of 14nm high-K/metal gate NMOS with taguchi method by Mah S.K., Ahmad I., Ker P.J., Tan K.P., Faizah Z.A.N.

Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device by Afifah Maheran A.H., Menon P.S., Ahmad I., Noor Faizah Z.A., Mohd Zain A.S., Salehuddin F., Sayed N.M.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling by Maheran A.H.A., Menon P.S., Ahmad I., Shaari S., Faizah Z.A.N.

Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method. by Afifah Maheran A.H., Firhat E.N., Salehuddin F., Mohd Zain A.S., Ahmad I., Noor Faizah Z.A., Menon P.S., Elgomati H.A., Roslan A.F.

Optimization of 10nm Bi-GFET Device for higher ION/IOFF ratio using Taguchi Method by Roslan A.F., Kaharudin K.E., Salehuddin F., Zain A.S.M., Ahmad I., Faizah Z.A.N., Hazura H., Hanim A.R., Idris S.K., Zaiton A.M., Mohamad N.R., Hamid A.M.A.