Search Results - 36570222300

Statistical process modelling for 32nm high-K/metal gate PMOS device by Maheran A.H.A., Noor Faizah Z.A., Menon P.S., Ahmad I., Apte P.R., Kalaivani T., Salehuddin F.

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Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method by Maheran A.H.A., Menon P.S., Shaari S., Kalaivani T., Ahmad I., Faizah Z.A.N., Apte P.R.

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Optimization of process parameters for threshold voltage and leakage current based on taguchi method by Noor Faizah Z.A., Ahmad I., Ker P.J., Menon P.S., Afifah Maheran A.H., Mah S.K.

Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

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Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

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Vth and ILEAK Optimization using taguchi method at 32nm bilayer graphene PMOS by Noor Faizah Z.A., Ahmad I., Ker P.J., Menon P.S., Afifah Maheran A.H.

Design and optimization of 22nm NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Majlis B.Y., Salehuddin F.

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Scaling down of the 32 nm to 22 nm gate length NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Elgomati H.A., Majlis B.Y., Salehuddin F.

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Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

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Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

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Modeling of 14 nm gate length n-Type MOSFET by Faizah Z.A.N., Ahmad I., Ker P.J., Roslan P.S.A., Maheran A.H.A.

Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method by Maheran A.H.A., Menon P.S., Shaari S., Ahmad I., Faizah Z.A.N.

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Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Salehuddin F., Mohd A.S., Noor Z.A., Elgomati H.A.

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Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device by Afifah Maheran A.H., Menon P.S., Ahmad I., Noor Faizah Z.A., Mohd Zain A.S., Salehuddin F., Sayed N.M.

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Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device by Roslan A.F., Salehuddin F., Zain A.S.M., Kaharudin K.E., Mohamad N.R., Maheran A.H.A., Haroon H., Razak H.A., Idris S.K., Ahmad I.

Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Salehuddin F.

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Development of process parameters for 22 nm PMOS using 2-D analytical modeling by Maheran A.H.A., Menon P.S., Ahmad I., Shaari S., Faizah Z.A.N.

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Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Salehuddin F., Mohd Zain A.S.

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Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method. by Afifah Maheran A.H., Firhat E.N., Salehuddin F., Mohd Zain A.S., Ahmad I., Noor Faizah Z.A., Menon P.S., Elgomati H.A., Roslan A.F.

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Threshold voltage optimization in a 22nm High-k/Salicide PMOS device by Afifah Maheran A.H., Menon P.S., Ahmad I., Yusoff Z.

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