Search Results - 36536722700

Design and optimization of 22nm NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Majlis B.Y., Salehuddin F.

Scaling down of the 32 nm to 22 nm gate length NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Elgomati H.A., Majlis B.Y., Salehuddin F.

Application of Taguchi method in the optimization of process variation for 32nm CMOS technology by Elgomati H.A., Majlis B.Y., Ahmad I., Salehuddin F., Hamid F.A., Zaharim A., Apte P.R.

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Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage by Elgomati H.A., Majlis B.Y., Ahmad I., Salehuddin F., Hamid F.A., Zaharim A., Mohamad T.Z., Apte P.R.

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Characterization of fabrication process noises for 32nm NMOS devices by Elgomati H.A., Majlis B.Y., Ahmad I., Ziad T.

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Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Salehuddin F., Mohd A.S., Noor Z.A., Elgomati H.A.

Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Salehuddin F.

Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method by Elgomati H.A., Majlis B.Y., Ahmad I.

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Analyze of input process parameter variation on threshold voltage in 45nm n-channel MOSFET by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A., Elgomati H.A., Majlis B.Y.

Optimization of HALO structure effects in 45nm p-type MOSFETs device using taguchi method by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A., Elgomati H.A., Majlis B.Y., Apte P.R.

Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method. by Afifah Maheran A.H., Firhat E.N., Salehuddin F., Mohd Zain A.S., Ahmad I., Noor Faizah Z.A., Menon P.S., Elgomati H.A., Roslan A.F.

Modelling of process parameters for 32nm PMOS transistor using Taguchi method by Elgomati H.A., Majlis B.Y., Hamid A.M.A., Susthitha P.M., Ahmad I.

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Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array by Salehuddin F., Ahmad I., Hamid F.A., Zaharim A., Hamid A.M.A., Menon P.S., Elgomati H.A., Majlis B.Y., Apte P.R.

Cobalt silicide and titanium silicide effects on nano devices by Elgomati H.A., Majlis B.Y., Salehuddin F., Ahmad I., Zaharim A., Hamid F.A.

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Optimizing 35nm NMOS devices V TH and I LEAK by controlling active area and halo implantation dosage by Elgomati H.A., Majlis B.Y., Salehuddin F., Ahmad I., Zaharim A., Hamid F.A.

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