Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit
Current trend in Integrated Circuits (IC) implementation such as System-on-Chip (SOC) has contributed significant advantages in electronic product features such as high circuit performance with high number of functions, small physical area and high reliability. Therefore, including Built-In-Self-Te...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2002
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| Online Access: | http://psasir.upm.edu.my/id/eprint/18394/1/18394.pdf http://psasir.upm.edu.my/id/eprint/18394/ |
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