Design of 6-Stage Pipeline Processor

• Main Author: Teng, Wen Jun
• Format: Final Year Project / Dissertation / Thesis
• Published: 2021
• Subjects: TA Engineering (General). Civil engineering (General)
• Online Access: http://eprints.utar.edu.my/4281/1/17ACB01947_FYP2.pdf; http://eprints.utar.edu.my/4281/

This project is about the design and implementation of RISC 6-stage pipeline processor for academic purpose. The main objective of this project is to improve the performance of the current RISC32 5-stage pipeline processor that developed in Universiti Tunku Abdul Rahman which is under Faculty of Information Technology by increasing the stages from 5 stages to 6 stages. After reviewing the timing delay of each stage, the longest delay of the 5-stage pipeline processor is accessing the memory stage which will reduce the performance due to the imbalance among the pipeline stages. This longest delay will slow down the clock rate of the processor. Thus, this project is initiated to divide the memory unit (cache) into 3 stages. Cache unit access will require 3 clock cycles if cache hit detection occur. Some modifications on cache unit were done to increase the performance of the performance. The instruction cache is pipelined at the appropriate location while distributing the components among 3 stages to achieve a balance stage delay. This project is modelled using Verilog code and a test program will be developed to test the functionality and compatibility of the newly design pipelined cache unit and RISC32. Lastly, Xilinx Vivado is used to synthesis and implement it to get the timing delay of each stage.